I was wondering, is it possible to convert supply ripple to phase noise in dBc?

For example, if supply ripple on Vcp tranfers directly to the output of the charge pump, any voltage deviation (Vd) will cause a frequency shift at the VCO output of Kvco*Vd. Does this follow the relationship:
Noise dBc/Hz = -20log ( Fdev / 2*Fn) where Fdev is the frequency deviation equal to Kvco*Vd and Fn is the frequency of the noise component?

Obviously, if we know Kvco then we can specify the ripple required to satisfy a particular noise requirement. But, my question is, is the supply ripple attenuated in-loop by the loop gain (in dB)?

If this is the case, then the loop gain at Fn can be gotten from the closed loop plots.

With regards to pushing, noise on Vdd of the VCO will cause frequency deviation at the output of the VCO. Can this be converted to phase noise in the same way?

My ultimate goal is to achieve phase noise within 1dB of the SimPLL simulations but fear that supply ripple and noise on the Vt line will not allow this.

Thanks for your time,

regards,

Gav

Power supply noise is one factor that can cause increased phase noise above what modeling predicts. It is usually possible, however, to reduce the effects so they cause minimal increase in overall phase noise.

Starting with frequency pushing, there is no fundamental reason why the VCO power supply should be any noisier in the PLL circuit than when the VCO open loop phase noise was measured. Note: 3 terminal regulators are usually quite noisy, and a capacitance multiplier (see http://en.wikipedia.org/wiki/Capacitance_multiplier) is often used to clean them up.

Noise on the supply lines to the PLL chip is also significant, not only on the charge pump supply. Ideally the charge pump supply would not be sensitive as there is an infinite impedance (current sources) to the CP output, however practically there is capacitive coupling. More importantly, any modulation on the supply to the logic or the charge pumps can modulate the logic switching levels, potentially modulating the switching time. Thus it is important to have a clean supply to the PLL chip. Note that this is usually not as demanding as the VCO and most evaluation boards (that achieve the PLL chip phase noise specification) simply run the PLL chip from 3-terminal regulators with heavy capacitive bypassing local to the chip. Note that care should be taken when sharing this regulated output.

To your question, is noise generated by supply ripple attenuated by the loop, the answer is maybe. Any VCO phase noise generated by pushing is treated the same as normal VCO phase noise and inside the loop bandwidth it is attenuated. Edge jitter added inside the PLL chip on the VCO path is suppressed like VCO phase noise, any jitter added to the reference path (including phase detector and CP) is faithfully reproduced on the VCO inside the loop bandwidth and suppressed outside. Anything added to the loop filter is also reproduced on the VCO inside the loop bandwidth and suppressed outside. (This is how many modulation schemes work).

[edit] I'd like to change the comment on the loop filter noise, noise added at the input of the loop filter generally will have a low-pass response, i.e. be effective within the loop bandwidth, that added after the loop filter will have a high-pass response, i.e. have most effect outside the loop bandwidth.

See comment below.
[/edit]
Peter.

Thanks for the swift reply. That makes sense.

I have a feeling, one of our PCBs is picking up noise on the Vtune line and loop filter traces, as they are unfortunately long and cover large areas of the PCB due to a complex fast-lock scheme. We are seeing 10dB worse than simulated phase noise over the 1kHz to 1MHz offsets. Someone, sime time ago, decided it was better to have a long Vtune line than a long RF trace feedback path to the PLL. I'm not necessarily sure that was the right decision?

It is a very busy 10-layer PCB, however if noise on Vtune can only modulate the VCO within the loop bandwidth, I can't reconcile where this noise is coming from as we have all linear regulation on-board and no switchers. We have (several) >1GHz signals on board, plus a 20MHz clock, but nothing in the region of 1k-1MHz. Could it just be low frequency components of broadband noise or 1/f noise?

As always, many thanks for your advice.

Gav

I've changed my response above - noise added at the output of the loop filter will be much the same as VCO Phase Noise - and only be attenuated inside the loop bandwidth.

If you have a long Vtune line, I think it is best to keep some (or even most) of the low pass filtering of the loop filter for the far end of the line at the VCO. This may not be possible with a complex fast-locking scheme. Are you sending a good ground reference with the Vtune signal - I suspect you are with 10 layers. If it passes over a cut in the groundplane this would be nasty. Try replacing the trace with a piece of coax temporarily, or adding some low-pass filtering at the VCO end.

Can you turn off everything else to see what the PLL alone can do, or if not, cut their clock?

Is what you are seeing an increase in the in-band phase noise floor - i.e. the noise inside the loop bandwidth is flattish but 10dB higher than expected? If this is the case, check that you have adequate slew rate driving the VCO and reference inputs of the PLL chip.

Responses below:

"If you have a long Vtune line, I think it is best to keep some (or even most) of the low pass filtering of the loop filter for the far end of the line at the VCO."
--> We do have one RC pole at the input of the VCO. The longest trace length is from chip to loop filter so I guess that's not as bad as I first imagined.

"Are you sending a good ground reference with the Vtune signal"
--> a reasonable one. There is a coplanar type arrangement for it on layer 10 while it references a GND on layer 8. However, I've just notice a clock line in proximity to it on layer 9 unshielded, which could be the cause of some noise.

"Can you turn off everything else to see what the PLL alone can do, or if not, cut their clock?"
--> Possible but tricky!

"Is what you are seeing an increase in the in-band phase noise floor - i.e. the noise inside the loop bandwidth is flattish but 10dB higher than expected? If this is the case, check that you have adequate slew rate driving the VCO and reference inputs of the PLL chip."
--> Yes, but also outside of the loop bandwidth too! We are seeing -80dBc/Hz at 10kHz as opposed to -90 to -94dBc/Hz and -110 as opposed to -120dBc/Hz at 1MHz. How can we "sqaure-up" or improve the slew of the RF? We are driving the reference via a 74 series buffer to square it.

Thanks again,

Regards,

Gav

Flat phase noise in-band generally means that you have excess random timing jitter on some of your edges. State of the art -220dBc/Hz chip FOM means that there is about 1ps jitter on the clock edges. Generating this sort of waveform from a sinusoid is actually fairly difficult and has more to do with designing an LNA than a logic gate - so I'm a bit concerned about the 74 series chip you are using. I'd take your low-noise reference and feed it directly to the reference input of the PLL chip. What is your reference frequency and what is its broadband phase noise floor? What PLL chip are you using? What FOM do you need?

Well the in-band noise is not FLAT, but flat'ish, we can still see some reference noise close-in and a rise near the loop bandwidth point.

Broadband noise floor of the reference is about -165dBc/Hz and we use a XTAL clean-up filter for the reference to get better than -145dBc/Hz @ 10kHz. Reference is 30MHz but needs to be buffered as it's feeding 2 PLLs. We're using the ADF4108. The reference is buffered using a SN74AHC1G04DVBR as it's a sinusoidal OCXO type.

Figure of merit - I guess if we work backwards (for one example frequency) from -90dBc/Hz at 10kHz, PFD=5MHz, max N ratio = 280 then...
a FOM of -206dBc/Hz should do, so the -219 for the ADF4108 should be ample. With a -219FOM we should be seeing noise of the order of -103dBc/Hz but it's more like -85 or worse in some cases.

Thanks again,

Regards,

Gav

If the in-band noise is up (as well as the out-of-band) I'd suspect excess random timing jitter on either the VCO or reference, or possibly noise on the chip supply. Check that you have adequate amplitude driving the VCO input on the chip and haven't picked up any low frequency noise on that line (local high-pass filter at chip if necessary). Low frequency noise would affect the slicing level and create jitter. I guess you have no way of checking the jitter on the reference after the 74AHC gate, so I'd still try feeding a clean reference directly to the chip reference input (only needs 800mv p-p). Perhaps you could cobble in a second crystal oscillator, a signal generator is unlikely to have the low jitter you need. Try a separate, possibly battery-based, power supply for the chip and VCO.

the reference signal has about 235fs of jitter (integrating from 100Hz to 5MHz) after the 74 inverter and 110fs before so the additive jitter is 125fs. Negligible. Thew slew rate is over 600V/us.

I will investigate PSU noise and separate supplies next.

Additionally, we have observed "double-hump" shaped in-band phase noise, where a noise rise is eveident around the loop bandwitdth point AND much lower down (typically 10 to 30kHz). Have you ever seen this before?

It seems to get worse at low tuning voltages (where Kvco is high)

Could it be gain ripple in the op-amp (unlikely) or an unstable loop?

I think some dynamic Icp compenstation is necessary as we are deling with very wide bandwidth VCOs where Kvco varies between about 100 and 350MHz/V over the tuning range.

Thanks again,

regards,

Gav

The reference jitter numbers look OK, (but note that the buffer is adding 208fs of jitter).

If it is not the reference then check the VCO slicer, one way of doing this is to change the VCO level at the chip and see if the noise changes. If it doesn't, look elsewhere.

As far as your other questions are concerned, SimPLL will give accurate results on accurate data. If you are using measured VCO tuning data then the effects of the Kv variations will show up in the simulations.

Sorry if I'm being a bit slow, but where did the 208fs come from?

We put a 6dB pad on the feedback path, no change to the phase noise apart from about a dB worse in-band, 0.5dB better out of band, but this is more likely experimental variation as we have seen this much variance between measurements. We were slightly overdriving the RF input of the chip if anything so the slew-rate should be fine.

The Kv is modelled from a datasheet graph and it does reflect the bandwidth changes although it doesn't reflect the "double-hump" noise shape.

We have a high pass filter on the feedback path also, so shouldn't be picking up any LF noise. I will try to separate the supplies and let you know how I get on.

Thanks,

Gav

208 = sqrt(235^2 - 125^2) as the jitter added by the buffer is independent of the reference jitter.

It's hard to offer any more suggestions from a distance, if the phase noise / bandwidth looks wrong then check (preferably measure) your Kv and Icp.

Dramatically lowering the loop bandwidth can help determine as to whether the noise is coming from the VCO or being fed in the tuning port.

just started out doing PLL work myself and found this forum via ADIsimPLL.

Regarding this "doubler hump" you mentioned, a colleague had problems with this once, where he had a hump in the phase noise at around 7kHz offset, which I think was well outside the loop bandwidth.